Xref: utzoo comp.sys.hp:9098 comp.arch:22968 comp.sys.apollo:9189 Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!zaphod.mps.ohio-state.edu!wuarchive!udel!nigel.ee.udel.edu!mccalpin From: mccalpin@perelandra.cms.udel.edu (John D. McCalpin) Newsgroups: comp.sys.hp,comp.arch,comp.sys.apollo Subject: Re: New 110 MIPS HP Snake at under $10,000. Message-ID: Date: 28 May 91 21:22:23 GMT References: <2070@kuling.UUCP> <1991May28.191746.11508@chpc.utexas.edu> Sender: usenet@ee.udel.edu Followup-To: comp.sys.hp Organization: College of Marine Studies, U. Del. Lines: 25 Nntp-Posting-Host: perelandra.cms.udel.edu In-reply-to: gary@chpc.utexas.edu's message of 28 May 91 19:17:46 GMT >>>>> On 28 May 91 19:17:46 GMT, gary@chpc.utexas.edu (Gary Smith) said: Gary> I'm interested in the sustainable memory bandpass between the D-cache Gary> and main memory on the Snake series. Anyone know what it is? Can it Gary> sustain two 64-bit operands each clock? If not, we have one more CPU Gary> that can sit and wait for memory, right? Yes. The current HP9000/7x0 machines can effectively manage one 32-bit word per clock cycle from main memory to cache. I think they do this as one 64-bit word every other cycle. Since cache lines are 64 bytes long, and assuming an 8-cycle penalty for a cache miss, we get an estimate of the sustainable bandwidth between memory and D-cache of one 64-bit word every 4 clock cycles. This can be compared to the rate of one 64-bit word every 2 cycles on the IBM RS/6000-320 (the more expensive machines do a bit better). Since the HP machines run at about twice the clock speed of the IBM machines, one sees about the same absolute sustainable memory bandwidth, and similar performance on bandwidth-limited computations. -- John D. McCalpin mccalpin@perelandra.cms.udel.edu Assistant Professor mccalpin@brahms.udel.edu College of Marine Studies, U. Del. J.MCCALPIN/OMNET