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From: herod@convex.com (Cliff Herod)
Newsgroups: comp.arch,comp.sys.mips,comp.sys.dec
Subject: Re: The MIPS EXECUTE instruction
Message-ID: <1991May28.182625.15199@convex.com>
Date: 28 May 91 18:26:25 GMT
Article-I.D.: convex.1991May28.182625.15199
References: <1991May27.184311.11596@zeno.mn.org>
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In article <1991May27.184311.11596@zeno.mn.org> gene@zeno.mn.org (Gene H. Olson) writes:
>Looking through all the documentation I have been able to find
>on the MIPS processor (Including Gerry Kane's book) I haven't
>found a rule about putting a branch in a branch delay slot.
>
Actually, the MIPS R-series Architecture document says:

    2.7.  Jump and Branch Instructions (may be number differently in other eds.)

    All jump and branch instructions are implemented with a delay of exactly
    one instruction.  That is, the instruction immediately following a jump
    or branch (i.e. occupying the "delay slot") is always executed while the
    target instruction is being fetched from storage.  It is not valid for
    a delay slot to be occupied itself by a jump or branch instruction;
    however this error is not detected, and the results of such an operation
    are undefined.

>	
>So, you MIPS software development guys, how about you put it
>in the assembler?

What happens to your trick when the R4000 comes along with three delay slots?