Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!uunet!stanford.edu!neon.Stanford.EDU!rfrench
From: rfrench@neon.Stanford.EDU (Robert S. French)
Newsgroups: comp.arch
Subject: Re: iWARP notes... it's pretty neat
Keywords: iWARP, parallel processing, vlsi,
Message-ID: <1991May31.184221.8054@neon.Stanford.EDU>
Date: 31 May 91 18:42:21 GMT
References: <uh311ae.675674229@sunmanager> <1991May31.134645.23455@bernina.ethz.ch> <frazier.675710376@oahu>
Organization: Computer Science Department, Stanford University, Ca , USA
Lines: 22

For people who want more information on the iWarp, here are some
recent papers that are relevant:

Shekhar Borkar, et al.  "Supporting Systolic and Memory Communication
in iWarp".  ISCA '90, pp 70-81.

Robert Cohn, et al.  "Architecture and Compiler Tradeoffs for a Long
Instruction Word Microprocessor".  ASPLOS '89, pp 2-14.

Ping-Sheng Tseng.  "Compiling Programs for a Linear Systolic Array".
PLDI '90, pp 311-321.  (Really talks about Warp, the the techniques
are probably applicable to iWarp)

If you take the last two papers together, you get a compiler that does
instruction scheduling, software pipelining, and automatic breakup of
tasks across a linear systolic array.  Now if only Intel could do
that...

BTW, I will be working with an iWarp system soon, and would enjoy
getting in contact with any of y'all who are currently using one.

			Rob