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From: george@ole.UUCP (George Lippincott)
Newsgroups: comp.lang.vhdl
Subject: Overloading signal assignments
Message-ID: <1988@ole.UUCP>
Date: 6 Jun 91 00:34:28 GMT
Organization: Seattle Silicon Corp., Bellevue, WA.
Lines: 26




   VHDL allows overloading of arithmetic and logic operators, but not the
assignment operator.  It seems like the ability to overload these operators
would be a useful feature.  This would allow automatic type-conversion
between various signal or variable types.  This would solve several problems
that I am running in to.  For example, say I am trying to write a behavioral
model for an n-bit wide flip-flop with a clear option.  To perform the clear
operation, I would like to say  Q <= "0";.   Unfortunately, the width of Q is
passed in using a generic and I don't think there is any way to control the
width of a literal.  If I could overload the "<=" operator I could use an
assignment function that automatically determined the width of the signal on
the left side and assigned a value to each bit. 
   Another place this comes up is if I write arithmetic functions that operate
on bit vectors or multi-valued-logic vectors.  Consider the following equation:

        sum <= A + B + cin 

   I have to somehow determine how many bits to return from the "+" operation
and this has to match the number of bits in sum.  If I could override the
"<=" operator, I could do sign-extension, truncation, or whatever is necessary
to make the number of bits match up.

   This seems like something that would be as easy to implement as any of the
other overloading.  Perhaps someone can comment on why this is not the case.