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From: cowgilc@prism.cs.orst.edu (Clayton Cowgill)
Newsgroups: comp.sys.amiga.graphics
Subject: Re: Idea for a graphics board
Keywords: 24 bit
Message-ID: <1991May30.030903.1920@lynx.CS.ORST.EDU>
Date: 30 May 91 03:09:03 GMT
References: <1991May28.191019.13406@nntp-server.caltech.edu> <479@regina.uregina.ca> <1991May29.212315.27847@nntp-server.caltech.edu>
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In <1991May29.212315.27847@nntp-server.caltech.edu> nygardm@nntp-server.caltech.edu (Michael T. Nygard) writes:

>I've been looking at some numbers on the board.  Here's what I came up with.

>Without using a CLUT (yuk.), assuming 80ns RAM, 1024x1024x24 resolution.

>1/(1024*1024*24*60) = .66227 ns/bit.
>(80 ns/cycle) / (.66227 ns/bit) = 120.8 bits/cycle

>That means a bus _at least_ 128 bits wide.  A 128 bit bus results in 5% of
>the memory cycles availible for the processor.

>Unless I go to video RAM, things could get unreasonable very fast.
>I know little about video RAM, could someone fill me in?

You might look at the TI34020 and its new FPU co-processor. It provides a lot
of the functionality of the i860, plus the posibility of TIGA compatibility.
The 34020 also has a 'smart' memory addressing system that can be used with
TI VRAMs- it radically improves memory access throughput.

4Meg sounds pretty thin for the kind of resolutions you're talking about. 
Monotors for a mega-pixel display are pretty expensive right now too... With
a little luck XGA will catch on in the PC world and monitor prices will come
down... 

The TI Graphics FPU (34082) has a 32MHz clock and will perform IEEE single
precision divide ops in 8 clock cycles and square root in 11 cycles. There
are 30 2-d and 3-d transforms in hardware with goodies like 1x4 and 4x4 
matrix operations and clipping. (for review, the 34020 allows 512Mbytes of
addressing, pixel processing, programmable video rates, etc...)

'Eh... Just my $.02

					-Clay

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Clayton Cowgill                                 cowgilc@prism.cs.orst.edu  
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