Xref: utzoo comp.sys.amiga.programmer:4185 comp.sys.amiga.hardware:9779 Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!uupsi!sunic!fuug!clinet!dix From: dix@clinet.fi (Risto Kaivola) Newsgroups: comp.sys.amiga.programmer,comp.sys.amiga.hardware,adsp.sw,adsp.hw Subject: Re: 68040 Compatibility Warning Message-ID: <1991Jun3.163847.10733@clinet.fi> Date: 3 Jun 91 16:38:47 GMT References: <22049@cbmvax.commodore.com> <1991Jun1.175626.3234@wintermute.north.de> Organization: City Lines Oy, Helsinki, Finland Lines: 31 kaba@wintermute.north.de (Kai Bartels) writes: >mks@cbmvax.commodore.com (Michael Sinz) writes: >>CopyBack. CopyBack means that when a program writes data to >>memory, it goes into the cache but *not* into the physical RAM. >>That means that if something was to read that RAM and it did not >>go through the data cache on the 68040, it will see old data. >>The two main examples of this are DMA devices and the instruction >>reading of the CPU itself. This means that even if the >Another important case where that mode can be deadly is in a multi-processor >machine. Has Motorola or C= taken any precautions in this direction. It'd be >really nice to run ADos2.0 or SVR4 on two or three processors! >Kai I thought that Motorola had implemented bus-snooping to maintain cache-coherency. Strangely enough, this can't keep the two caches coherent with regard to each other. In the event of an external write accessing cached memory 68040 invalidates the corresponding cache entry. I remember that I read in somewhere 68040 would be able to act as the "source" of data if an external bus master (such as another processor) wanted to read cached data. Please correct me if I'm wrong. Risto >-- >"I'm beat, I'm torn, Shattered and tossed and worn, Too shocking to see" >BITNET: g14b@dhbrrz41 + UUCP: kaba@wintermute.north.de >Snail: Kai Bartels + Hudemuehler Str. 37 + 2800 Bremen 41 + FRG -- Risto Kaivola (dix@clinet.fi) or (Risto.Kaivola@f123.n220.z2.FIDONET.ORG)