Xref: utzoo comp.sys.amiga.programmer:4206 comp.sys.amiga.hardware:9818 Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!batcomputer!cornell!uw-beaver!ubc-cs!alberta!aunro!ukma!rex!spool.mu.edu!sol.ctr.columbia.edu!lll-winken!sun-barr!rutgers!cbmvax!mks From: mks@cbmvax.commodore.com (Michael Sinz) Newsgroups: comp.sys.amiga.programmer,comp.sys.amiga.hardware,adsp.sw,adsp.hw Subject: Re: 68040 Compatibility Warning Message-ID: <22153@cbmvax.commodore.com> Date: 4 Jun 91 11:21:43 GMT References: <22049@cbmvax.commodore.com> <1991Jun1.175626.3234@wintermute.north.de> <1991Jun3.163847.10733@clinet.fi> Reply-To: mks@cbmvax.commodore.com (Michael Sinz) Organization: Commodore, West Chester, PA Lines: 46 In article <1991Jun3.163847.10733@clinet.fi> dix@clinet.fi (Risto Kaivola) writes: >kaba@wintermute.north.de (Kai Bartels) writes: > >>mks@cbmvax.commodore.com (Michael Sinz) writes: >>>CopyBack. CopyBack means that when a program writes data to >>>memory, it goes into the cache but *not* into the physical RAM. >>>That means that if something was to read that RAM and it did not >>>go through the data cache on the 68040, it will see old data. >>>The two main examples of this are DMA devices and the instruction >>>reading of the CPU itself. This means that even if the >>Another important case where that mode can be deadly is in a multi-processor >>machine. Has Motorola or C= taken any precautions in this direction. It'd be >>really nice to run ADos2.0 or SVR4 on two or three processors! > >>Kai > >I thought that Motorola had implemented bus-snooping to maintain >cache-coherency. Strangely enough, this can't keep the two caches >coherent with regard to each other. In the event of an external write >accessing cached memory 68040 invalidates the corresponding cache >entry. I remember that I read in somewhere 68040 would be able to >act as the "source" of data if an external bus master (such as another >processor) wanted to read cached data. Please correct me if I'm wrong. The 68040 can do this, if the bus is always connected to it. However, the Amiga bus design is actually a set of disjoint buses. This gives the system the ability to do a BLIT while DMA in Zorro-III space and still have the CPU run code out of motherboard RAM. That also means that not all bus transactions are seen by the 68040 so bus snooping is not possible. Also, the main warning is for the people who write programs that allocate and copy up code into memory. Since, as you have stated, the 68040 can not snoop between its own two caches, you need to flush the copyback data cache to make sure that it is in memory and then clear the instruction cache to make sure that it sees the new memory (just in case it was already in the cache) The 68040 in copyback mode will break 99.99% of any code that is self-modifying and does not do the CacheClearU() call in Exec. /----------------------------------------------------------------------\ | /// Michael Sinz - Amiga Software Engineer | | /// Operating System Development Group | | /// BIX: msinz UUNET: rutgers!cbmvax!mks | |\\\/// Programming is like sex: | | \XX/ One mistake and you have to support it for life. | \----------------------------------------------------------------------/