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From: grr@cbmvax.commodore.com (George Robbins)
Newsgroups: comp.sys.amiga.programmer,comp.sys.amiga.hardware,adsp.sw,adsp.hw
Subject: Re: 68040 Compatibility Warning
Message-ID: <22139@cbmvax.commodore.com>
Date: 4 Jun 91 02:10:40 GMT
References: <22049@cbmvax.commodore.com> <1991Jun1.175626.3234@wintermute.north.de> <1991Jun3.163847.10733@clinet.fi>
Reply-To: grr@cbmvax.commodore.com (George Robbins)
Organization: Commodore, West Chester, PA
Lines: 28

In article <1991Jun3.163847.10733@clinet.fi> dix@clinet.fi (Risto Kaivola) writes:
> kaba@wintermute.north.de (Kai Bartels) writes:
> 
> >mks@cbmvax.commodore.com (Michael Sinz) writes:
> 
> I thought that Motorola had implemented bus-snooping to maintain
> cache-coherency. Strangely enough, this can't keep the two caches
> coherent with regard to each other. In the event of an external write
> accessing cached memory 68040 invalidates the corresponding cache
> entry. I remember that I read in somewhere 68040 would be able to
> act as the "source" of data if an external bus master (such as another
> processor) wanted to read cached data. Please correct me if I'm wrong.

The root problem is that Motorola's mental memory model doesn't seem
to include the I=D=virtual=real=supervisor=user mode that AmigaDOS
requires, but is oriented towards a more general "unix" model.

In some ways, the AmigaDos software model represents an arbitrary
"simple machine" model that could be mapped fairly closely to the
original 68000 hardware, but is still not 100% inline with the
overall 680X0 family architecture as it has developed. This does not
keep it from working, but makes it requires more work and sometimes
compromises to take advantage of new architectural features.

-- 
George Robbins - now working for,     uucp:   {uunet|pyramid|rutgers}!cbmvax!grr
but no way officially representing:   domain: grr@cbmvax.commodore.com
Commodore, Engineering Department     phone:  215-431-9349 (only by moonlite)