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From: rhyde@hubbell.ucr.edu (randy hyde)
Newsgroups: comp.sys.apple2
Subject: Re: RISC systems
Message-ID: <14869@ucrmath.ucr.edu>
Date: 31 May 91 18:48:41 GMT
References: <782@generic.UUCP>
Sender: news@ucrmath.ucr.edu
Reply-To: rhyde@hubbell.ucr.edu (randy hyde)
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BTW, the 486 manual from Intel lists one or two instructions as having
zero cycle instruction times (obviously, the instr opcode must be in
the cache for this to occur).