Path: utzoo!utdoe!generic!pnet91!ericmcg
From: ericmcg@pnet91.cts.com (Eric Mcgillicuddy)
Newsgroups: comp.sys.apple2
Subject: Re: RISC systems
Message-ID: <804@generic.UUCP>
Date: 2 Jun 91 15:45:03 GMT
Sender: root@generic.UUCP
Organization: People-Net [pnet91], Etobicoke, ON
Lines: 16

>BTW, the 486 manual from Intel lists one or two instructions as having
>zero cycle instruction times (obviously, the instr opcode must be in
>the cache for this to occur).
>From: rhyde@hubbell.ucr.edu (randy hyde)

That is because the 486 uses some RISC architecture features, as do the '030
and '040. (don't recall if the '020 was pipelined). A pipeline is different
from a cache, but the idea is the same even if the implementation is not. 

By and large RISC processors have taken over the microprocessor market, there
are very few "CISCs" still being designed. At the heart of every new processor
is a RISC processor wrapped in microcode to maintain compatibility with the
installed base.

UUCP: bkj386!pnet91!ericmcg
INET: ericmcg@pnet91.cts.com