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From: mrj@cluster.cs.su.oz.au (Mark James)
Newsgroups: sci.electronics
Subject: Question about Page Mode DRAMs
Message-ID: <2484@cluster.cs.su.oz.au>
Date: 1 Jun 91 08:07:03 GMT
Organization: Dept. of Comp. Science, Uni of Sydney, Australia
Lines: 7

In data books, page mode DRAM accesses are always shown as
a sequence of read, write or read-modify-write cycles.
Is it possible to arbitrarily interleave reads and writes
during the RAS pulse?  If so, what is the timing?
If not, why not?

Mark