Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!mips!dimacs.rutgers.edu!rutgers!cbmvax!daveh
From: daveh@cbmvax.commodore.com (Dave Haynie)
Newsgroups: comp.arch
Subject: Re: ACE (Was Re: Will NeXT survive?  Grow with the times?)
Message-ID: <22236@cbmvax.commodore.com>
Date: 7 Jun 91 05:07:59 GMT
References: <11399@uwm.edu> <32580026@hpcuhe.cup.hp.com> <4638@batman.moravian.EDU> <22152@cbmvax.commodore.com> <863@taniwha.UUCP>
Reply-To: daveh@cbmvax.commodore.com (Dave Haynie)
Organization: Commodore, West Chester, PA
Lines: 43

In article <863@taniwha.UUCP> paul@taniwha.UUCP (Paul Campbell) writes:
>In article <22152@cbmvax.commodore.com> daveh@cbmvax.commodore.com (Dave Haynie) writes:
>>In article <4638@batman.moravian.EDU> halkoD@batman.moravian.EDU (David Halko) writes:
>>>> peter da silva writes:
>>>> Is this true?  I understand that NeXT uses a 25MHz NuBus (2.5 times the NuBus
>>>> used in the Mac II series).  

>>Actually, I've heard both that the NeXT uses a 25MHz NuBus clock and that it
>>uses a 12.5MHz NuBus clock.  Anyone know for certain?

>Yeah, they do both, the basic bus is a 12.5MHz NuBus (12.5/25 is a 'nice'
>number if you have a 25MHz CPU - everything is synchronous) - they have a
>special burst mode which is clocked at 25MHz - the bus has 2 clocks 12.5/25.

OIC.  So this is a special mode over and above the NuBus "block transfer".

>NuBus 90 has picked up the Next clocking/burst scheme (it is a nice design)
>and added it to existing NuBuses at 10/20MHz (for compatability).

I had read something about an enhanced NuBus being supported by Apple some time
in the future, but I had no idea where it came from.  So this clocking scheme
is fully upward compatible and all?  Sounds like a pretty cool solution.  And
although I still prefer asynchronous buses, a 20-25MHz bus running synchronous
to your local bus is certainly no slouch, at least for a PC/PW system.

>Next solve this by driving everything with the CMOS driver ICs, having short
>backplanes and requiring the driver/controller chips to be physically right
>next to the bus. The also terminate it so that it gets exactly one reflection
>within the bus settling time.

Sounds about right.  I stayed away from CMOS buffers on the Amiga 3000 bus
(though some of the signals are driven by a CMOS ASIC), mainly for speed 
concerns, though I was also worried about noise.  We had to stay with TTL
levels for compatibility reasons, but the buffer drive, speed, and backplane
termination was chosen for support of the 32 bit bus.  Nowadays, with FCT 
and ACTQ parts being pretty common, even in the relatively weird types like
74x646, I'll probably use TTL-level CMOS buffers in the future.  Though I
just got some samples of these new "FR" parts....

-- 
Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests"
   {uunet|pyramid|rutgers}!cbmvax!daveh      PLINK: hazy     BIX: hazy
	"This is my mistake.  Let me make it good." -R.E.M.