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From: noah@cs.washington.edu
Newsgroups: comp.arch
Subject: N11 - i860 XP - some details, who knows more?
Message-ID: <1991Jun7.193507.3733@beaver.cs.washington.edu>
Date: 7 Jun 91 19:35:07 GMT
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Organization: Computer Science & Engineering, U. of Washington, Seattle
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Originator: noah@sole.cs.washington.edu


	I just heard a few things about the i860 XP (formerly known as
the N11) from an Intel person.  This is the successor to i860 and was
announced last week (probably overshadowed by the Touchstone and TMI
announcements).  It is binary code compatible.  It uses the same basic
architecture with the following differences.

	The caches are bigger.  I-cache is 16K (v. 4K).  The D-cache is
also 16K (v. 8K).  The burst mode to memory is 400 MB/sec (the old one
was around 150-160 MB/sec?).  There is something built-in to facilitate
a snoopy cache scheme.  There are also some enhancements for dealing with
fault tolerance.  The first version is to run at 50 MHZ and then there
will be a 66 MHZ one.  It is implemented 0.8 micron technology.

	This is all the information I have.  Does anyone know any more?
Among the many complaints that have surfaced about the i860, a major one
is the memory bandwidth being inadequate, especially for keeping the
floating point pipeline fed.  Is this really going to help?  They have
doubled the D-cache size, but 16K is still small.  What about this burst
mode?  I am not familiar with it in the i860.  Is increasing its speed
2.5 times going to make a difference in trying to get near peak floating
point performance?

						Rick N. Zucker
						noah@cs.washington.edu