Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!uunet!zephyr.ens.tek.com!tektronix!reed!intelhf!ichips!ichips!glew From: glew@pdx007.intel.com (Andy Glew) Newsgroups: comp.arch Subject: Re: MIPS LL & SC instrs Message-ID: Date: 9 Jun 91 18:19:23 GMT References: <24990@samsung.samsung.com> <4411@spim.mips.COM> Sender: news@ichips.intel.com (News Account) Organization: Intel Corp., Hillsboro, Oregon Lines: 28 In-Reply-To: cprice@mips.com's message of 7 Jun 91 04:52:26 GMT >A note on caching and coherence: For regular addresses on the MIPS >processors, whether the a reference to the address is cached or not is >determined on a per-virtual-page basis by a bit in the TLB entry. >Your typical user page is cached. LL/SC only works on locations >accessed though the cache. For processors with cache coherence (The >R6000A used in the R6000-based multiprocessor that CDC has been >talking about and the R4000) the same thing holds true -- the >coherence applied to an access is a property of the >virtual-to-physical translation. LL/SC only works on locations that >are marked coherent (and therefore kept up to date with memory by >hardware). > >-- >Charlie Price cprice@mips.mips.com (408) 720-1700 >MIPS Computer Systems / 928 Arques Ave. MS 1-03 / Sunnyvale, CA 94088-3650 Q: what does MIPS do for synchronization through uncached memory? E.g. synchronization with an I/O device? Or are all I/O devices cache consistent? -- Andy Glew, glew@ichips.intel.com Intel Corp., M/S JF1-19, 5200 NE Elam Young Parkway, Hillsboro, Oregon 97124-6497 This is a private posting; it does not indicate opinions or positions of Intel Corp.