Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!mips!spool.mu.edu!olivea!uunet!ogicse!qiclab!nosun!loop!keithl
From: keithl@loop.uucp (Keith Lofstrom;;;628-3645)
Newsgroups: comp.lsi
Subject: Want power-on-reset cell for CMOS LSI
Message-ID: <1991Jun6.215934.11851@loop.uucp>
Date: 6 Jun 91 21:59:34 GMT
Organization: KLIC
Lines: 17

I'm building a full-custom CMOS circuit for a client, and need a power on
reset cell.  You know, logic 0 out until the supply exceeds the trip level,
then logic 1 until the supply goes delta below the trip level.

I've come up with one, but I know I could do much better with more time.
Rather than spend more time (pretty expensive right now) I thought I'd find
out if anyone knows of any papers or other descriptions of such beasts.  I
don't want to futz with bandgaps and resistive dividers.  Just something
simple, well controlled, low power at full supply, using P and N fets only,
and already demonstrated.

Thanks;

-- 
Keith Lofstrom  keithl@loop.uucp ...!sun!nosun!loop!keithl (503)628-3645
KLIC --- Keith Lofstrom Integrated Circuits --- "Your Ideas in Silicon"
Design Contracting in Bipolar and CMOS - Analog, Digital, and Power ICs