Newsgroups: comp.lsi.testing
Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!caen!ox.com!math.fu-berlin.de!unidui!veit
From: veit@du9ds3.uni-duisburg.de (Holger Veit)
Subject: HL Description for ISCAS89 Benchmarks available?
Message-ID: <veit.676191831@du9ds3>
Summary: <- This word means "Summary" :-)
Keywords: ISCAS89,HL Descriptions
Sender: @unidui.uni-duisburg.de
Organization: Rechenzentrum Uni-Duisburg
Date:  6 Jun 91 07:03:51 GMT
Lines: 29


Some of the ISCAS'89 benchmark circuits were created by a synthesis
algorithm from a high level description. Examples are s208, s838, s344
and (probably) s1423. Some of them also have a distinct "function" that can
be expressed by few statements in a HL form. Examples are again
s208 (8 bit programmable clock divider), s838 (32 bit version of s208) and
s344 (4x4 Bit shift&add multiplier).

Automated test patteren generation (especially for sequentially deep circuits)
would be easier if the function were known. This is the main advantage a
test engineer has: he knows how the circuit has to be initialized, driven,
what's observable, etc.

Are there HL descriptions (in any HDL for instance: VHDL,Verilog,ISPS,etc.)
for at least some of the benchmark circuits (I know that the largest circuits
were real designs but were modified by exchange of components, so there are
none with exact function).

This request goes especially to the (anonymous) contributors of the circuits.

Please help.

Holger Veit

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