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From: preston@ll.mit.edu (Steven Preston)
Newsgroups: comp.sys.amiga.hardware
Subject: Building genlock for A500
Message-ID: <9106101133.AA28256@LL.MIT.EDU>
Date: 10 Jun 91 15:33:42 GMT
Sender: daemon@cis.ohio-state.edu
Distribution: comp
Organization: The Ohio State University Department of Computer and Information Science
Lines: 12

I am assembling a genlock for an A500 and need to know the
requirements for taking control of the system clock through the video
port.  Specifically, how long can the system clock be halted without
interrupting things like RAM refresh cycles?

There is no documentation on this in either the Amiga service manual
or hardware reference guide.

Also, any information on Amiga genlock hardware design in general
would be greatly appreciated.
--
Steve Preston  (preston@ll.mit.edu)