Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!mips!cprice From: cprice@mips.com (Charlie Price) Newsgroups: comp.arch Subject: Re: MIPS LL & SC instrs Message-ID: <4561@spim.mips.COM> Date: 11 Jun 91 04:52:42 GMT References: <24990@samsung.samsung.com> <4411@spim.mips.COM> Sender: news@mips.COM Organization: MIPS Computer Systems, Inc Lines: 51 Nntp-Posting-Host: lloyd.mips.com In article glew@pdx007.intel.com (Andy Glew) writes: > >>A note on caching and coherence: For regular addresses on the MIPS >>processors, whether the a reference to the address is cached or not is >>determined on a per-virtual-page basis by a bit in the TLB entry. >>Your typical user page is cached. LL/SC only works on locations >>accessed though the cache. For processors with cache coherence (The >>R6000A used in the R6000-based multiprocessor that CDC has been >>talking about and the R4000) the same thing holds true -- the >>coherence applied to an access is a property of the >>virtual-to-physical translation. LL/SC only works on locations that >>are marked coherent (and therefore kept up to date with memory by >>hardware). > >Q: what does MIPS do for synchronization through uncached memory? >E.g. synchronization with an I/O device? Or are all I/O devices >cache consistent? I'm not quite sure I understand the question. Do you mean synchronization in access to device registers? LL/SC exist to provide a means for mutual exclusion among "consenting adults". Cache coherence is the mechanism that the processor has available to tell it when a shared data item has been modified by another (coherent) access in the system. LL/SC are basically only useful for lock words among processors. If a smart I/O controller needed to participate in mutual exclusion, I guess you would have to make the answer up depending on what the I/O controller and/or it's memory were able to do. The devices for this system are probably on the VME bus, so any onboard memory they had wouldn't know about our coherency. I/O (DMA) is (normally) coherent. Cache coherence is done by two parts: 1) The cache controller (in this case, on chip like all MIPS processors) that issues requests (like "I want to read this cache line and own it") and can service external requests (like "invalidate this location"). 2) Some external mechanism to accept requests from the processors and service requests for coherent memory operations. In our case, this is a custom snoopy bus-interface chip. The memory and I/O adapter cards are hooked up to the system backplane with Bus Interface Chips, so I/O operations can be made cache coherent. I hope I managed to stumble across what you were actually asking -- if not, try again. -- Charlie Price cprice@mips.mips.com (408) 720-1700 MIPS Computer Systems / 928 Arques Ave. MS 1-03 / Sunnyvale, CA 94088-3650