Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!news.cs.indiana.edu!ux1.cso.uiuc.edu!uxa.cso.uiuc.edu!msp33327 From: msp33327@uxa.cso.uiuc.edu (Michael S. Pereckas) Newsgroups: comp.arch Subject: Re: IEEE arithmetic (Goldberg paper) Message-ID: <1991Jun12.014403.18508@ux1.cso.uiuc.edu> Date: 12 Jun 91 01:44:03 GMT References: <9106112357.AA18157@ucbvax.Berkeley.EDU> Sender: usenet@ux1.cso.uiuc.edu (News) Organization: University of Illinois at Urbana Lines: 22 In <9106112357.AA18157@ucbvax.Berkeley.EDU> jbs@WATSON.IBM.COM writes: > I said: >>If your chip has 80 bit registers I fail to see how you can avoid >>performing 80 bit loads and stores while saving and restoring these registers. > David Chase said: >Other people have managed in the past. Perhaps you are insufficiently >imaginative. > Perhaps not. Of course one way people have managed in the past >is to only save and restore the first 64 bits of the register. In my >view this demonstrates excessive imagination. > James B. Shearer Although 80 bit in-register intermediates can be useful, if all 80 bits aren't saved during context switches, you end up with random precision, and no one will be very happy. There have been machines in the past with this problem, if I remember correctly. -- < Michael Pereckas <> m-pereckas@uiuc.edu <> Just another student... > "This desoldering braid doesn't work. What's this cheap stuff made of, anyway?" "I don't know, looks like solder to me."