Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!sdd.hp.com!elroy.jpl.nasa.gov!ncar!gatech!prism!mailer.cc.fsu.edu!uflorida!travis!hardy!dana From: dana@hardy.hdw.csd.harris.com (Dan Aksel) Newsgroups: comp.arch Subject: Re: IEEE arithmetic (Goldberg paper) Message-ID: <3646@travis.csd.harris.com> Date: 12 Jun 91 13:12:30 GMT References: <9106112357.AA18157@ucbvax.Berkeley.EDU> Sender: news@travis.csd.harris.com Organization: Harris Computer Systems, Ft. Lauderdale, FL Lines: 20 In article <9106112357.AA18157@ucbvax.Berkeley.EDU> jbs@WATSON.IBM.COM writes: > > I said: >>If your chip has 80 bit registers I fail to see how you can avoid >>performing 80 bit loads and stores while saving and restoring these registers. >----------------------------------------------------------- > Perhaps not. Of course one way people have managed in the past >is to only save and restore the first 64 bits of the register. In my >view this demonstrates excessive imagination. > James B. Shearer Solution is relatively simple. Hardware provides a status register which indicates the precision of each register. A computed GOTO tells which format to save each individual register in. This may create too much overhead if a rapid context switch time is the critical path instead of memory space. THe only compromise I can see immediately is a two bit status field which tells the precision of the LARGEST format currently stored in the register file. All registers are then saved in this format. Not an optimal solution but it works. --- Dan AKsel