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From: hrubin@pop.stat.purdue.edu (Herman Rubin)
Newsgroups: comp.arch
Subject: Re: IEEE arithmetic (Goldberg paper)
Summary: Simpler hardware solutions
Message-ID: <13498@mentor.cc.purdue.edu>
Date: 13 Jun 91 11:19:02 GMT
References: <9106112357.AA18157@ucbvax.Berkeley.EDU> <3646@travis.csd.harris.com>
Sender: news@mentor.cc.purdue.edu
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In article <3646@travis.csd.harris.com>, dana@hardy.hdw.csd.harris.com (Dan Aksel) writes:
> In article <9106112357.AA18157@ucbvax.Berkeley.EDU> jbs@WATSON.IBM.COM writes:

| >          I said:
| >>If your chip has 80 bit registers I fail to see how you can avoid
| >>performing 80 bit loads and stores while saving and restoring these registers.
| >-----------------------------------------------------------
| >          Perhaps not.  Of course one way people have managed in the past
| >is to only save and restore the first 64 bits of the register.  In my
| >view this demonstrates excessive imagination.
| >                          James B. Shearer

> Solution is relatively simple.  Hardware provides a status register which
> indicates the precision of each register.  A computed GOTO tells which format to
> save each individual register in.  This may create too much overhead if a rapid
> context switch time is the critical path instead of memory space.
> 
> THe only compromise I can see immediately is a two bit status field which tells
> the precision of the LARGEST format currently stored in the register file.  All
> registers are then saved in this format.  Not an optimal solution but it works.
For saving and restoring individual 80-bit registers, why not use either a 64+16or a 96 or even 128 bit memory unit?  If a bunch of registers are to be saved, 
to be restored later, the hardware could set up the blocks of 16 and 64 bit
pieces.
-- 
Herman Rubin, Dept. of Statistics, Purdue Univ., West Lafayette IN47907-1399
Phone: (317)494-6054
hrubin@l.cc.purdue.edu (Internet, bitnet)   {purdue,pur-ee}!l.cc!hrubin(UUCP)