Path: utzoo!dciem!array!colin
From: colin@array.UUCP (Colin Plumb)
Newsgroups: comp.arch
Subject: Faster busses are hard; can we do wider?
Message-ID: <1940@array.UUCP>
Date: 13 Jun 91 16:44:27 GMT
Organization: Array Systems Computing, Inc., Toronto, Ontario, CANADA
Lines: 44

I'm trying to evaluate the feasability of some >1000 line buses
prefessionally, so I'm making this blatant effort to pick the net's
brains.

At the last ASPLOS, Howard Davidson <hld@sun.com> gave a nifty tutorial
on the state of the art in fitting more into a smaller space and
(partially consequently) making it go faster.  More transistors per
debuggable unit requires more testing facilities such as boundary scan,
denser and faster requires better cooling than casually forced air,
and wire delays become ever more significant.

He was really big on multi-chip modules, which are basically miniature
PC boards on which bare dice are mounted.  You get shorter wire lengths,
better thermal properties, finer pitch, and the like.  You also get
repair and debugging problems since you can't just stick a logic analyzer
on everything so easily.

Then there's the inter-board communications problem.  Past 100 MHz, it
gets rather painful, so there's a lot of pressure to widen instead
of hastening system busses.  (Witness the 256-bit maximum Futurebus+
width.)

Cinch Coinnectors make a tangled-wire-bump called the Synapse that has
gorgeous electrical properties (.5 nH per pin) and they pack on 40 mil
centres, about 1 mm.  100 connectors per square cm makes massively
wide data buses feasable.

Another company called Betaphase make a sort of ribbon cable (it's actually
a flexible PC board) which clamps onto gold fingers at the edge of a PC board
and provides 125 connectors per inch, per side.

And apparently AMP have somkething in the works, too.  Probably others.

Has anyone played with this stuff?  Is it available, does it work?  How
do *you* get enought data to your screaming wonder to keep it from
starving?  Just talking to a cache at >1GB/sec is hard work.  And even
with a cache, a dozen processors or so will ask for a heck of a lot of
bandwidth out of main memory.  Widening it to a full (secondary) cache
line is is an easy way out (or so we think) if only the connector
technology can manage it.

Would anyone like to share experiences, opinons, or prejudices?
-- 
	-Colin