Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!samsung!umich!umeecs!msi.umn.edu!cs.umn.edu!kksys!edgar!orac!bret From: bret@orac.UUCP (Bret Indrelee) Newsgroups: comp.arch Subject: Re: MIPS LL & SC instrs Summary: Non-cached memory I would like sync primitives to work on Message-ID: <373@orac.UUCP> Date: 13 Jun 91 00:36:13 GMT References: <4411@spim.mips.COM> <1991Jun10.182119.5523@dvorak.amd.com> Organization: Technix Inc., Saint Paul MN, USA Lines: 32 In article <1991Jun10.182119.5523@dvorak.amd.com> peter@nucleus.amd.com (Peter Song) writes: >In article glew@pdx007.intel.com (Andy Glew) writes: >| >| >... LL/SC only works on locations that >| >are marked coherent (and therefore kept up to date with memory by >| >hardware). >| > >| >-- >| >Charlie Price cprice@mips.mips.com (408) 720-1700 >| >| Q: what does MIPS do for synchronization through uncached memory? > >What are the circumstances where one has to use non-cacheable memory locations for any >"meaningful" (meaningful being more than just the producer/consumer relationship) >synchronization, given that LL/SC works only with cacheable locations? What if you had a non-cacheable, shared memory on the system bus. It is possible to make a shared memory that links multiple systems to a single coherent memory image. Not all the processors sharing the memory would be on a single chassis. If you had a bus that depended on snooping/snarfing to maintain the cache-coherence, you would have to mark this shared memory as non-cacheable. (It can be modified without a local bus access being generated, so there is nothing to snoop/snarf.) -Bret -- ------------------------------------------------------------------------------ Bret Indrelee | Our mail is still somewhat unreliable. Sorry. uunet.uu.net!cs.umn.edu!kksys!edgar!orac!bret -And still trying