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From: crisp@mips.com (Richard Crisp)
Newsgroups: comp.arch
Subject: Re: HP PA-RISC Cache Question
Message-ID: <4755@spim.mips.COM>
Date: 15 Jun 91 02:13:08 GMT
References: <1991Jun13.221247.6855@jetsun.weitek.COM> <8840036@hpfcso.FC.HP.COM>
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In article <8840036@hpfcso.FC.HP.COM> maf@hpfcso.FC.HP.COM (Mark Forsyth) writes:
>>From: lupin@jetsun.weitek.COM (Edward Lupin)
>>
>>
>I don't think that anyone at HP is willing to describe any unpublished
>technical details, especially in an area considered to be a competitive
>advantage. Unfortunately in this respect, the RISC processor market is
>still a competitive business.  The only thing that can be said is that no 
>laws of physics are being violated, that there is plenty of timing margin
>to insure reliability and manufacturability, and that the viability of
>large primary caches (off-chip) for high-performance RISC was generally
>written off prematurely by some of the industry (or at least according to
>technical articles published in the last couple of years).  
>

What Mark doesn't want to say is that HP figured out that they could calculate
an address in half of a pipeline stage. They simply allow something like
1 and 1/2 pipe stages for a cache access. 
-- 
		    Richard Crisp              crisp@mips.com
		MIPS Computer Systems        !decwrl!mips!crisp
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