Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!wuarchive!uunet!mcsun!hp4nl!cbmnlu1!cbmnlux!ecl014!ronald From: ronald@ecl014.UUCP (Ronald van Eijck) Newsgroups: comp.sys.amiga.hardware Subject: Re: 68040 Compatibility Warning Message-ID: Date: 5 Jun 91 17:03:45 GMT References: <22049@cbmvax.commodore.com> <1991Jun1.175626.3234@wintermute.north.de> <1991Jun3.163847.10733@clinet.fi> Organization: R&R Software Lines: 23 In article <1991Jun3.163847.10733@clinet.fi> dix@clinet.fi (Risto Kaivola) writes: > >I thought that Motorola had implemented bus-snooping to maintain >cache-coherency. Strangely enough, this can't keep the two caches >coherent with regard to each other. In the event of an external write >accessing cached memory 68040 invalidates the corresponding cache >entry. I remember that I read in somewhere 68040 would be able to >act as the "source" of data if an external bus master (such as another >processor) wanted to read cached data. Please correct me if I'm wrong. > >Risto Kaivola (dix@clinet.fi) or (Risto.Kaivola@f123.n220.z2.FIDONET.ORG) Thats exactly what I read about 6 months ago in a german magazine. They had about 15 pages on the 68040 and this feature was discribed in there. So long, -- +-------------------------------------------------------------------------+ | Ronald van Eijck {eunet!}hp4nl!cbmnlux!ecl014!ronald | | | | We do the impossible at once for a miracle we need a little more time | +-------------------------------------------------------------------------+