Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!mips!ptimtc!nntp-server.caltech.edu!toddpw
From: toddpw@nntp-server.caltech.edu (Todd P. Whitesel)
Newsgroups: comp.sys.apple2
Subject: Re: What mem.chips go in the ZIP cache?
Message-ID: <1991Jun12.074733.7196@nntp-server.caltech.edu>
Date: 12 Jun 91 07:47:33 GMT
References: <1991Jun10.231828.16904@risky.ecs.umass.edu> <1991Jun11.040640.3827@nntp-server.caltech.edu> <petroski.676690862@mwunix.mitre.org>
Organization: California Institute of Technology, Pasadena
Lines: 8

petroski@mwunix.mitre.org (Frank Petroski) writes:

>I take it one must yank out the 8K SRAMS and replace them with the 32K SRAMS?

Yep. Mixing chip sizes won't work, as the cache size must be a power of 2.

Todd Whitesel
toddpw @ tybalt.caltech.edu