Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!mips!pacbell.com!att!ucbvax!IFI.UIO.NO!larserio From: larserio@IFI.UIO.NO (LarsErikOsterud) Newsgroups: comp.sys.atari.st Subject: Re: Mega STe processor speed switch Message-ID: Date: 12 Jun 91 00:10:51 GMT Sender: daemon@ucbvax.BERKELEY.EDU Reply-To: larserio@ifi.uio.no Lines: 27 Here are routines for switching both MEGA STE and HYPERCAHE between 16 Mhz with cache and 8 Mhz without cache.... The subroutines cache_on and cache_off must be called from inside supervisor mode as they access restricted adresses. cache_on: cmpi.b #2,$2.w ;TOS 2.xx (MEGA STE) ? bne.s hyper_on ;No, Hypercache on bset.b #1,$FFFF8E21.w ;Yes, 16 Mhz speed bset.b #0,$FFFF8E21.w ;Switch cache on rts cache_off: cmpi.b #2,$2.w ;TOS 2.xx (MEGA STE) ? bne.s hyper_off ;No, Hypercache off bclr.b #0,$FFFF8E21.w ;Yes, Cache off bclr.b #1,$FFFF8E21.w ;Switch to 8 MHz rts hyper_on: move.l #$1E0040,-(sp) ;GPO signal on = Hypercache on bra.s set_cache hyper_off: move.l #$1DFFBF,-(sp) ;GPO signal off = Hypercache off set_cache: trap #14 ;Xbios addq.l #4,sp rts Lars-Erik / ABK-BBS +47 2132659 / ____ ______ ________________________ Osterud / larserio@ifi.uio.no / /___ / The norwegian ST __________/ ______________________/ ____/ / Klubben, user association