Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uwm.edu!linac!att!att!cbnewsl!wkk
From: wkk@cbnewsl.att.com (wesley.k.kaplow)
Newsgroups: comp.arch
Subject: CISC vs. RISC Code Sizes
Keywords: CISC RISC Size CRISP MIPS R3000
Message-ID: <1991Jun18.132315.8202@cbnewsl.att.com>
Date: 18 Jun 91 13:23:15 GMT
Organization: AT&T Bell Laboratories
Lines: 75

Well, although I do not have data from one of the more popular CISC
machines, I do have data on the AT&T CRISP processor compared to the
MIPS R2000, R3000 processors. 

Introduction:
What I say here is for CODE SIZE only and says nothing about whether
the CRISP processor itself is a CISC or RISC processor.  CRISP does however
distinguish itself from most 'RISC' processor in that CRISP has three
instruction code sizes, 2, 6, and 10 bytes.  The MIPS processor has only
once size, 4 bytes.  Also, like a CISC processor, CRISP is not a load/store
machine in that is has a basically othagonal instruction-set in addressing
modes.

Benchmarks:
Several benchmarks where used to determine the static code size data.  These
include the following groups:

	1) Dhrystone
	2) Real Program (RP) - 9 Unix programs
		cat, comm, diff, echo, mv, nroff, pr, rm, wc
	3) BSC - 7 Benchmarks
		Ackermann's, Word Count, Quick Sort, TTY driver,
		Symbol Table Insert, Buffer Manipulation, Statistic
		

Method:
The compiler for the MIPS processors was the UMIPS-BSD 1.0 system.
This did contain an optimizing compiler, but not an optimizing linker.
The compiler for the CRISP was an internal research compiler.

Results:
		Benchmark	MIPS Code Size/CRISP Code Size
		----------------------------------------------
		   BSC			    1.83
		Dhrystone		    1.84
		   RP			    1.67

In more detail it was found that 70% of CRISP instruction were of the
2-byte form and the remaining 30% of the 6-byte form.  Therefore, the
average CRISP instruction size was 3-3.4 bytes/instructions while MIPS
is 4 bytes/instruction. 


As well as bytes/instruction average, we compared the static instruction
count as well.  In our study we found that:

		Extra Instructions % in MIPS = 44%.

By combining this static instruction increase with the larger bytes/instruction
number, we also come to approximately the same ~1.7x larger code size
for MIPS.


Conclusion:
This work was done 4 years ago and therefore the MIPS compiler may have
improved.  Processors like the CRISP in terms of instruction encoding
(i.e., they have many shorter than 4-byte instruction codings) may also
show similar results,  since many 'CISC' processors usually have instructions
that have 2 or even 3 regiester-based instructions, and the MIPS 
instructions are always 4-byte regardless of the number of operands. 
Also, like a CISC processor CRISP has a basically 'orthagonal' instruction
set, unlike the general RISC load/store type architecture.
I think these results may be representative for architectural reasons.
Once again I remind everybody in NetLand, I am not presenting any claims
as to the performance characteristics of the processors above.


with disclamer;
use disclamer;


Wesley Kaplow
AT&T Bell Laboratories
Whippany, NJ
201-386-4634