Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!mips!zaphod.mps.ohio-state.edu!cis.ohio-state.edu!ucbvax!hplabs!hpcc05!hpcuhb!hpcuhe!sramesh From: sramesh@hpcuhe.cup.hp.com Newsgroups: comp.arch Subject: Re: What is the ratio of programs sizes CISC versus RISC Message-ID: <32580034@hpcuhe.cup.hp.com> Date: 18 Jun 91 15:17:42 GMT References: Organization: HP/MSL Lines: 30 / hpcuhe:comp.arch / rwallace@unix1.tcd.ie (russell wallace) / 7:25 pm Jun 16, 1991 / "RISC" these days is not to be taken very literally. Most modern RISC processors have: lots of 32-bit registers orthogonal 3-operand instructions load/store with powerful addressing modes and optional sign-extension on loads integral floating-point on the SPARC, function calls with parameter passing in a single instruction on several RISC chips, every instruction can be conditional on one of the status bits, and can optionally set the status register Therefore, a program on a modern "RISC" chip takes fewer instructions (usually by about 30% or so) than the same program on a 680x0 or 80x86. However because every instruction on a RISC chip is 32 bits wide whereas some instructions on a 680x0 are only 16 bits and a few on an 80x86 are only 8 bits (e.g. RET), the object file will probably be larger to the tune of 10-15% ... in other words, not a significant difference. "To summarize the summary of the summary: people are a problem" Russell Wallace, Trinity College, Dublin rwallace@unix1.tcd.ie ----------