Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!spool.mu.edu!uunet!mcsun!ukc!mucs!mshute From: mshute@cs.man.ac.uk (Malcolm Shute) Newsgroups: comp.lsi.cad Subject: Re: State Machine Compilers Message-ID: <2715@m1.cs.man.ac.uk> Date: 18 Jun 91 10:50:31 GMT References: <21422@cadillac.CAD.MCC.COM> <10809@idunno.Princeton.EDU> Sender: news@cs.man.ac.uk Reply-To: mshute@cs.man.ac.uk (Malcolm Shute) Organization: Department of Computer Science, University of Manchester UK Lines: 17 In article <10809@idunno.Princeton.EDU> miyazaki@taichung (Takeshi Miyazaki) writes: >Is there any state assignment program which can reduce finite state machine? >(reduce the number of states and generate equivalent FSM) It's probably not what you were asking for (since it was only a 'toy' research package): but does anyone know if anything commercially usable came out of an M.Sc. thesis by Simon Finn (1983) of the Programming Research Group (Oxford University)... he used Mary Sheeran's HDL (called uFP) to describe a simple Minsky machine, going through the same sort of process as Mead and Conway (1980) did in section 6.2 of their book (An Introduction to VLSI Systems)... i.e. Starting with the processor described as a single, massive FSM, it was mathematically decomposed into a network of much smaller FSMs (e.g. the PC, and PSW could be broken off from the main loop, and then the register bank, etc). -- Malcolm SHUTE. (The AM Mollusc: v_@_ ) Disclaimer: all