Path: utzoo!utgpu!news-server.csri.toronto.edu!qucdn!leek Organization: Queen's University at Kingston Date: Monday, 17 Jun 1991 13:15:12 EDT From: Message-ID: <91168.131512LEEK@QUCDN.QueensU.CA> Newsgroups: comp.sys.amiga.audio Subject: Re: CHEAP 16-bit STEREO sound samplers References: <91166.165734DXB132@psuvm.psu.edu> <39yN41w164w@bluemoon.uucp> <1991Jun17.150054.27117@cunews.carleton.ca> In article <1991Jun17.150054.27117@cunews.carleton.ca>, ags@scs.carleton.ca (Alexander G. M. Smith) says: > >The parallel port can go very fast, assuming that it is like the old CIA >chips in the C64, at least a megahertz (one million read a byte >operations per second). The 8250 is running as a synchronous 68xx peripherial chip off the 7MHz 68000. Since the synchronous bus cycles has to sync up to E clock which is about 7.14MHz/10 = 714KHz , the actual bus cycles varies. The best you can hope to do is limited to ~ 700K/sec. That is without any other overheads - no handshakes, no store overheads etc. > The bottleneck seems to be more with the >software reading from it (unless you are using an A3000). Figure that >you have to toggle a control line to pick which half of 16 bits is read >/ latched: 2 instructions per word read. Then there's the reading, >another two instructions. The IO ports are not as fast as main memory. You are looking at about 20 states or 10 clock cycles at least per port access. (Since I don't have the 68000 data sheet with me, I can only quote from my memory.) > Storage takes another three, two for mixing >the bytes into a word and one for saving and incrementing the storage >pointer. Another two are needed for testing if you have filled your >recording buffer. So, that's 9 instructions per word. Each instruction >takes, what, 4 clock cycles (one or two to read the op code, another >couple to read or write the data). So, that's ballpark 40 clock cycles. >On an 8MHz machine, that's 200,000 word size samples per second. > >Of course, if your hardware handshaking gets complicated, it will slow >things down. Especially when the port access cost a lot of CPU cycles. If you opt for something like a FIFO chip ($20 U.S. for a 4K FIFO0 and trigger A/D conversion with a hardware clock, then the software overhead can be made much lower. Each time when the FIFO gets half filled, you just go out and read data off with a blind transfer with no handshake overhead... With these extra hardware, 2 channel 16-bit 44KHz samples are feasible. > >- Alex K. C. Lee