Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!usc!zaphod.mps.ohio-state.edu!think.com!snorkelwacker.mit.edu!ai-lab!rice-chex!bson
From: bson@rice-chex.ai.mit.edu (Jan Brittenson)
Newsgroups: comp.sys.handhelds
Subject: Re: hp48 speed
Message-ID: <16525@life.ai.mit.edu>
Date: 16 Jun 91 23:12:07 GMT
References: <31342@hydra.gatech.EDU> <1991Jun15.101631.24453@corpane.uucp> <43378@cup.portal.com>
Sender: news@ai.mit.edu
Organization: nil
Lines: 20

In a posting of [16 Jun 91 17:05:12 GMT]
   Jake-S@cup.portal.com (Jake G Schwartz) writes:

 > Bill also mentioned in Philly back last November that the guys had
 > experimented with an implementation of a subset of the RPL system on
 > an 8088 machine, and that they had achieved a 2-to-1 speedup.

   Maybe, but the Saturn CPU today is only a cell in a custom chip,
no? Since given the instruction timings it seems to be a 4-bit CPU
(although with a 64-bit architecture), it is probably a fairly small
cell as well. I'm sure that if there were space for it, a huge speed
gain could be made by widening the external data bus and making all
internal data paths (and the ALU) 20 bits (5 digits).

   For numerical crunching, the 64-bit architecture certainly is just
great. Perhaps microcoded (up to full 64-bit) multiplication and
division could improve trig and log speeds.

						-- Jan Brittenson
						   bson@ai.mit.edu