Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!convex!mic!letni!utacfd!merch!cpe!adaptex!adaptx1!neese From: neese@adaptx1.UUCP Newsgroups: comp.sys.ibm.pc.hardware Subject: Re: Unix on 486 Machines Message-ID: <284500026@adaptx1> Date: 14 Jun 91 19:36:48 GMT References: <6408@w20-575-117.MIT.EDU> Lines: 40 Nf-ID: #R:w20-575-117.MIT.EDU:6408:adaptx1:284500026:000:1932 Nf-From: adaptx1.UUCP!neese Jun 14 08:58:00 1991 >>There are two major differences in running UNIX on an ISA and an EISA >>bus. ... > >>The second thing is that EISA boards provides significantly better performance >>in a network than ISA machines. > >You may be right, but it might be useful if you gave some detail as to why >EISA network adapters would be better. The potential reasons I see are: > > 1) EISA has a better bus mastering scheme. > 2) The data path is wider. > 3) The data rate can be higher. > >But, then you'd have to support these reasons with measurements or more >detailed models. For example, I'd like to know how many commercial protocol >stacks for 486 machines are capable of maxing out the ethernet with an EISA >interface. >If your TCP stack just can't pump data down to the bus adapter >fast enough or, more likely, it can't receive it fast enough, maybe you're >OK with the (cheaper ?) ISA interface. There is more to it than that. I doubt very many TCP implementations, under UNIX and Novell, for example could max out the bandwidth of the wire, but there are other considerations. Using the 32 bit EISA bus and bus mastering, the ethernet card would utilize less of the bus I/O time, therefore allowing more time for other I/O (such as disk) to occur. This is more relevant in a multi-tasking environment, but something to consider. So many have looked at the EISA implementation from the perspective of, "WOW, now I can move data at 33MBytes/sec!" Well, this isn't very pratical given the current state of I/O adapters/controllers and the peripherals that exist today (and for some time on the future). But with that speed and a proper buffering implementation on the adapter/controller, more I/O's can be generated per slot than could ever be done on the ISA architecture. Just something to consider. Roy Neese Adaptec Senior SCSI Applications Engineer UUCP @ neese@adaptex uunet!cs.utexas.edu!utacfd!merch!adaptex!neese