Newsgroups: comp.arch
Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!wuarchive!uunet!stanford.edu!leland.Stanford.EDU!jackk
From: jackk@leland.Stanford.EDU (Jack Kouloheris)
Subject: Re: Three-Level Metal
Message-ID: <1991Jun21.175207.23634@leland.Stanford.EDU>
Organization: AIR, Stanford University
Date: Fri, 21 Jun 91 17:52:07 GMT
Lines: 18

In article <13560@pt.cs.cmu.edu> lindsay@gandalf.cs.cmu.edu (Donald Lindsay) 
writes:
>I notice that the new i860 is built with a 3-level-metal process.
>
>I recall that Motorola promised to build the 88110 this way,
>and someone posted here expressing disbelief.
>
>So, is the i860 really the first? And how many of the upcoming
>superscalars will be three layer?
>-- 
>Don		D.C.Lindsay 	Carnegie Mellon Robotics Institute

The RS/6000 chipset was built using a 3 layer metal process...the
third layer, in this case, being used for power distribution and
attachment to the C4 flip-chip solder bumps. (The I/Os are located
are distributed in the middle of the chip rather than being restricted
to the periphery)