Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!mcsun!ukc!inmos!gimli!roger
From: roger@gimli.inmos.co.uk (Roger Shepherd)
Newsgroups: comp.arch
Subject: Re: Three-Level Metal
Message-ID: <16748@ganymede.inmos.co.uk>
Date: 21 Jun 91 20:00:39 GMT
References: <13560@pt.cs.cmu.edu>
Sender: news@inmos.co.uk
Reply-To: roger@gimli.inmos.co.uk (Roger Shepherd)
Organization: INMOS Limited, Bristol, UK
Lines: 19

In article <13560@pt.cs.cmu.edu>, lindsay@gandalf.cs.cmu.edu (Donald
Lindsay) writes:

|> I notice that the new i860 is built with a 3-level-metal process.

|> I recall that Motorola promised to build the 88110 this way,
|> and someone posted here expressing disbelief.

|> So, is the i860 really the first? And how many of the upcoming
|> superscalars will be three layer?

The T9000 transputer (which is superscalar - with a vengence) uses a 
3-level-metal process.  I would expect a significant number of
the next generation of processors to be implemented on three (or more) layer 
metal processes.  High density, high connectivity, three layer processes, 
like that used for the T9000, offer very high transistor density; they 
are very attractive for large scale logic devices.

Roger Shepherd - roger@inmos.co.uk or roger@inmos.com