Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!cis.ohio-state.edu!pacific.mps.ohio-state.edu!linac!att!princeton!taichung!miyazaki From: miyazaki@taichung (Takeshi Miyazaki) Newsgroups: comp.arch Subject: Re: Three-Level Metal Message-ID: <11073@idunno.Princeton.EDU> Date: 22 Jun 91 21:56:01 GMT References: <1991Jun21.175207.23634@leland.Stanford.EDU> Sender: news@idunno.Princeton.EDU Organization: Princeton University Lines: 11 Nntp-Posting-Host: taichung.princeton.edu Three-Level Metal for ECL (R6000) is not intresting. ECL Gate Array is built using Three-Level since several years ago. Because of large power consumption. But Three-Level Metal for CMOS is intresting. Is is also for power line? Takeshi Miyazaki miyazaki@ee.princeton.edu