Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!mips!pacbell.com!ucsd!nosc!baron!ryptyde!dant
From: dant@ryptyde.UUCP (Daniel Tracy)
Newsgroups: comp.sys.amiga.advocacy
Subject: Re: The Amiga's Future
Message-ID: <89@ryptyde.UUCP>
Date: 22 Jun 91 09:52:03 GMT
References: <#g1H3+$o@cs.psu.edu> <12901@uwm.edu> <22308@cbmvax.commodore.com> <1991Jun11.134256.9465@cs.mcgill.ca> <1134@stewart.UUCP> <59@ryptyde.UUCP> <1146@stewart.UUCP>
Reply-To: dant@ryptyde.UUCP (Daniel Tracy)
Organization: Ryptyde Timesharing (ryptyde.cts.com)
Lines: 17

Responding to the following:

"Look at it this way -- the 80286 has 4 segment registers, just as you said,
and each segment is no more than 64KB in length, but it can still physically
address 16MB, and its maximum virtual address space is 1GB."

I understand that, on the 286, the segment registers (in 16-bit protected
mode) are used as pointers to a table of 24-bit addresses, and that's how
it addresses 16MB. However, I don't understand the underlying difference
between accessing physical memory and virtual memory. That is, why one
should be less limited than the other. Maybe I should take a class on
CPU design and not bug you guys about it. I also don't understand how
it can address 16384 segments if it only has 6 segment registers!
(each one-bit, right? Or is that where my mistake is?)

But what really intruiged me is that the 68000 line also had a segmented
memory model (?). How does this work? It also has 4 segment registers?