Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!IRO.UMontreal.CA!matrox!altitude!menzies From: menzies@CAM.ORG (Stephen Menzies) Newsgroups: comp.sys.amiga.hardware Subject: Re: Fusion-40, the 68040 Card for A2000 avail... Message-ID: <1991Jun25.212433.24418@CAM.ORG> Date: 25 Jun 91 21:24:33 GMT References: <1991Jun20.114837.22962@unibi.uni-bielefeld.de> <1991Jun21.183207.27427@CAM.ORG> <22645@cbmvax.commodore.com> Organization: Altitude.CAM.ORG, St-Lambert QC CANADA Lines: 100 mks@cbmvax.commodore.com (Michael Sinz) writes: > [Much stuff deleted] >>In article <1991Jun21.183207.27427@CAM.ORG> menzies@CAM.ORG (Stephen Menzies) writes: >>>markus@techfak.uni-bielefeld.de (Markus Illenseer) writes: >>>The Processor is working internally with a Tact-Rate of 50 Mhz, though the >>>external Rate will be 25 MHz. >Hold on... Just because the CPU wants a 50MHz input clock does not mean >that you can call it 50MHz tact-rate. The reason you place a 50MHz clock >into the chip is such that it can have a stable. 25MHz clock to play with. >In fact, some designs have 100MHz clocks going through a divider to bring >the 50MHz clock into the CPU. This is again to provide a stable clock. >The 68040 (chip) currently is only available at 25MHz. Anything trying to >imply 50MHz is pulling someone's chain. Also, any attempt to go beyond >that clock rate is *VERY* dangerous and should be looked at as suspect. >(The 68040 is built to a rather tight spec and that includes the clock) Due to the Technical nature of this discussion I have directed these questions to the attention of RCS and asked for *their* reply. RCS (verbatum) reply: [quote]From the mc68040 users manual see 8-1 bus characteristics. Take it to mean what you want, but the fusion-forty at present is a 25mhz design for the amiga2000. "the mc68040 uses two clocks to generate timing - a bus clock(bclk) and a processor clock(pclk). the pclk signal is exactly twice the frequency of the bclk signal and is internally phase-locked to bclk and distributed throughout the device to generate timing for all logic blocks. the bclk signal is only used as the reference signal for the phase-lock-loop (pll), which synchronize the pclk. the use of the dual clock inputs allows the bus interface to operate at half the speed of the internal logic of the of the processor, requiring less stringent memory interface requirments. since the rising edge of bclk is used as the reference point for the pll, all timing specs are referenced to this edge."[unquote] >>The RCS board fits into the A2000 processor slot. The board runs at 1750 >>Drystones/mip using Amiga Bench Drystone Rating. This translates to >?^^^^^^^^^^^^^? >>31650 Drystones/sec. Users can expect a much better rating once popular >>softwares are optimized for the 040. The board has been running under the >>2.0 OS and I might add, the present software runs even more reliably than >>under 1.3. For one, the Copyback caches can remain on ALL the time. The 2.0 >>OS seems to have been developed with the 040 in mind. >Ok, so what is that? A MIP is already rather silly measurement and then >adding a Drystones/mip? Where did that come from? Current testing shows >that a standard Drystones compiled by standard C with no special 68040 >optimizations comes out to 23,000 to 25,000 rating if the 68040 caches >are full on and CopyBack mode is enabled. A smarter compiler (68040 smart) >would be able to make this number higher, but there are very few compilers >out there that can do this and even fewer products compiled with them. Again, RCS's reply: [quote]With regards to mips and dhrystones according to ibm and everex advertising 1 mips (vax mips) is considered to be 1750 dhrystone per second,therefore 10 mips is considered to be 17500 dhrystone per second.[unquote] >[stuff deleted] > However, some applications >may not be ready for 68040 and CopyBack. CopyBack tends to make programs >that write code to RAM not work too well since even if the instruction cache >is flushed, the new code may not have been copied to physical RAM from >the cache.[more stuff deleted] And Again, RCS's reply: [Quote]Copyback will work very well with programs that are copied to ram, however instead of flushing the instruction cache, flush the data cache before you addtask(). this must work,period. If you cannot see this working I strongly suggest that you read the 68040 users manual.[unquote] --------end of RCS replies------------- And I repeat, I am NOT an employee of RCS though I have been independently testing the Fusion_40 for a couple of weeks now, in particular, with 3D Animation software. I am willing though to relay questions of a technical nature direcly to them. --stephen >/----------------------------------------------------------------------\ >| /// Michael Sinz - Amiga Software Engineer | >| /// Operating System Development Group | >| /// BIX: msinz UUNET: rutgers!cbmvax!mks | >|\\\/// | >| \XX/ Quantum Physics: The Dreams that Stuff is made of. | >\----------------------------------------------------------------------/ -- Stephen Menzies Email: menzies@CAM.ORG