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From: bson@rice-chex.ai.mit.edu (Jan Brittenson)
Newsgroups: comp.sys.handhelds
Subject: Re: C compiler for HP48SX
Keywords: C compiler
Message-ID: <16627@life.ai.mit.edu>
Date: 24 Jun 91 05:11:11 GMT
References: <NVxHUKy.677729692@l_eld07.icaen.uiowa.edu>
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In a posting of [24 Jun 91 02:14:52 GMT]
   caeaves@icaen.uiowa.edu (Cory A Eaves) writes:

 > How about it?  Anyone interested helping with this project?  I have
 > experience with compilers but not a lot with the HP.  Any HP gurus
 > interested?

   I looked at GCC, and quickly gave up on this. It seemed impossible
to create a machine description for the Saturn. The biggest obstacle
problem is that the Saturn screws up register allocation - the
registers don't interact orthogonally. A, B, and C often interact
freely with each other, while D often only interacts with C. See ADD,
for instance. Registers R0-R4 are used for storage only; no arithmetic
available.  Only registers A and C interact with memory, via D0 or D1.
The interaction patterns also vary from instruction to instruction.
There are bit operators, but only for the low 16 bits. 8 levels of
hardware stack, although a stack could be emulated using D0 or D1.
Which leaves only one register. 

   Things get messy real quickly. Adapting GCC to the Saturn is an
order of magnitude more difficult than adapting it to the 8086! But
then I don't know much about GCC. It may be doable.

   On the other hand, I'm sure there are compilers that are easier to
adapt (with a substantial recoding effort), but GCC is attractive
since you only need to do it *once*, in the back-end descriptions and
then reuse it with F77, Pascal, whatever, front-ends. And GCC is free.

   There is a way out: have GCC produce code for a highly orthogonal,
target machine. Something like a 64-bit PDP-11 with 20-bit addressing
and variable-size instructions (varying by the nybble). Then use an
interpreter on the HP-48 to implement this machine and run the code.
Sort of like the p-code idea, except we're talking about a register
machine of course.  Say a machine with 256 64-bit registers, or other
architectural features that studiously allows the compiler to fully
explore its optimizing potential. Sure, you lose a lot in the
interpretation, but will regain some (to be taken literally) by the
improved optimization.

   Finally, according to RMS, GCC *is* capable of producing a
pseudo-code intended primarily for C interpreters. I'm not sure how
well suited it is for implementation on the HP-48. Besides,
brain-storming wild CPU designs is half the fun! :-)

						-- Jan Brittenson
						   bson@ai.mit.edu