Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!wuarchive!waikato.ac.nz!ldo
From: ldo@waikato.ac.nz (Lawrence D'Oliveiro, Waikato University)
Newsgroups: comp.sys.mac.programmer
Subject: Parity (was Re: Mac SIMMs vs. IBM-compatible SIMMs)
Message-ID: <1991Jun24.175014.4049@waikato.ac.nz>
Date: 24 Jun 91 17:50:14 +1200
References: <1991Jun20.191113.8626@gn.ecn.purdue.edu> <25625@well.sf.ca.us>
Organization: University of Waikato, Hamilton, New Zealand
Lines: 16

Let's see, typical error rates for computer storage are one incorrect
bit read out of 10 ** 12.

Adding a parity bit detects half of these errors, so the number
of undetected errors drops to one in 2 * 10 ** 12.

Now, considering that you're using 12.5% more chips to achieve this
(plus interface circuitry circuitry and, of course, the error detection
support), is it worth it?

Lawrence D'Oliveiro                       fone: +64-71-562-889
Computer Services Dept                     fax: +64-71-384-066
University of Waikato            electric mail: ldo@waikato.ac.nz
Hamilton, New Zealand    37^ 47' 26" S, 175^ 19' 7" E, GMT+12:00
To someone with a hammer and a screwdriver, every problem looks
like a nail with threads.