Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!mips!ptimtc!nntp-server.caltech.edu!gbrown
From: gbrown@nntp-server.caltech.edu (Glenn Christopher Brown)
Newsgroups: comp.sys.mac.programmer
Subject: Re: Parity (was Re: Mac SIMMs vs. IBM-compatible SIMMs)
Message-ID: <1991Jun24.075635.14865@nntp-server.caltech.edu>
Date: 24 Jun 91 07:56:35 GMT
References: <1991Jun20.191113.8626@gn.ecn.purdue.edu> <25625@well.sf.ca.us> <1991Jun24.175014.4049@waikato.ac.nz>
Organization: California Institute of Technology, Pasadena
Lines: 32

ldo@waikato.ac.nz (Lawrence D'Oliveiro, Waikato University) writes:

>Let's see, typical error rates for computer storage are one incorrect
>bit read out of 10 ** 12.

>Adding a parity bit detects half of these errors, so the number
>of undetected errors drops to one in 2 * 10 ** 12.

>Now, considering that you're using 12.5% more chips to achieve this
>(plus interface circuitry circuitry and, of course, the error detection
>support), is it worth it?

	Parity checking in 8 bit systems detects all 1 bit errors within a byte.
Parity checking is only fooled when there are an even number of errors in
a byte(including in the parity bit).  This
means the chance that parity checking will be fooled is on the order
of 9*8 chances in (10^12)^2 or _approximately_ 1 chance in 10^22. (This
is the probability that 2 errors will occur at distinct locations in the
same 9 bit byte).
	That means errors are about 10 billion times less likely to go
undetected.  Not just 2 times less likely.

	Whether knowing when 9,999,999 out of 10,000,000 errors occurs is
actually worth the cost of the extra chips is another question entirely.
(Note: The cost increase is more than just 12.5% more chips:  Much extra glue
logic must be implemented in order to take advantage of the extra bit...
especially since 9bit TTL doesn't exist! (to my knowledge))
	I personally don't think it's worth it:  How many compu. companies
do you know of who implement parity checking in memory storage?  

--Glenn Brown
gbrown@tybalt.caltech.edu