Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!swrinde!mips!apple!well!nagle
From: nagle@well.sf.ca.us (John Nagle)
Newsgroups: comp.sys.mac.programmer
Subject: Re: Parity (was Re: Mac SIMMs vs. IBM-compatible SIMMs)
Message-ID: <25673@well.sf.ca.us>
Date: 25 Jun 91 18:17:47 GMT
References: <1991Jun20.191113.8626@gn.ecn.purdue.edu> <25625@well.sf.ca.us> <1991Jun24.175014.4049@waikato.ac.nz> <1991Jun24.075635.14865@nntp-server.caltech.edu>
Lines: 18

gbrown@nntp-server.caltech.edu (Glenn Christopher Brown) writes:

>ldo@waikato.ac.nz (Lawrence D'Oliveiro, Waikato University) writes:

>>Let's see, typical error rates for computer storage are one incorrect
>>bit read out of 10 ** 12.

      Gee, if it's that bad, my IIci is getting a bad bit every two hours
or so, assuming 3 MIPS and two 32-bit memory accesses (one instruction,
one data) per instruction.

>	I personally don't think it's worth it:  How many compu. companies
>do you know of who implement parity checking in memory storage?  

      IBM, Compaq, ...  All those guys who are bigger than Apple.
Why do you think SIMMs are designed for 9 chips?

					John Nagle