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From: jdg@cs.man.ac.uk (Jim Garside)
Newsgroups: comp.arch
Subject: Re: Branchless conditionals
Message-ID: <2795@m1.cs.man.ac.uk>
Date: 26 Jun 91 10:01:11 GMT
Article-I.D.: m1.2795
References: <1991Jun14.173510.22510@dg-rtp.dg.com> <32580036@hpcuhe.cup.hp.com> <13947@mentor.cc.purdue.edu>
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Reply-To: jdg@cs.man.ac.uk (Jim Garside)
Organization: Department of Computer Science, University of Manchester UK
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Since no one has mentioned it, the ARM - a modern RISC processor - has
conditional execution of *all* its instructions.

Jim Garside