Path: utzoo!dciem!array!colin From: colin@array.UUCP (Colin Plumb) Newsgroups: comp.arch Subject: Re: What is the ratio of programs sizes CISC versus RISC Message-ID: <1980@array.UUCP> Date: 27 Jun 91 20:48:38 GMT References: Organization: Array Systems Computing, Inc., Toronto, Ontario, CANADA Lines: 16 In article rwallace@unix1.tcd.ie (russell wallace) writes: >"RISC" these days is not to be taken very literally. Most modern RISC >processors have: > > load/store with powerful addressing modes and optional sign-extension on > loads Er... come again? Some RISCs (e.g. 290x0) have just register indirect, most have just register+offset, some can scale the register, the i860 has postincrement, and the ARM has fairly powerful post/pre-indexing features. But none of these compare to what the VAX or 680[234]0 can do. Even the 8086's and 68000's reg+reg+offset is more than any RISC chip I know of does. Do you feel like defending that claim? -- -Colin