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From: twolf@cs.utah.edu (Tom Wolf)
Subject: Re: Papers on low power digital circuits
Date: 28 Jun 91 09:49:13 MDT
Message-ID: <1991Jun28.094913.17801@hellgate.utah.edu>
Organization: University of Utah CS Dept
References: <42494@ucbvax.BERKELEY.EDU>

In article <42494@ucbvax.BERKELEY.EDU> luciano@canuck.Berkeley.EDU (Luciano Lavagno) writes:
>Any pointer ? Design tricks, theoretical analyses, synthesis
>methodologies:
>everything is welcome ! I am especially interested in CMOS, by the
>way...

What about Asynchronous CMOS design? Martin at Cal Tech, Ginosar at Technion,
and I have all built CMOS circuits using Async design instead of clocked.
My results seem to agree with thiers, in that the circuits run over a wide
voltage range. Mine run between 0.70 volts and 5.5 volts (as high as my
tester goes). Of course, there is a greater than 10x performance difference.

Still, at less than 1.0 volts, they aren't using much power.

Tom