Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!mips!pacbell.com!ucsd!nosc!baron!ryptyde!dant From: dant@ryptyde.UUCP (Daniel Tracy) Newsgroups: comp.sys.amiga.advocacy Subject: Re: 680x0 vs 80x86 Message-ID: <132@ryptyde.UUCP> Date: 28 Jun 91 08:00:08 GMT References: <92@ryptyde.UUCP> <4671.tnews@templar.actrix.gen.nz> <1154@stewart.UUCP> <1991Jun25.165516.13021@mintaka.lcs.mit.edu> <1991Jun27.064123.27492@neon.Stanford.EDU> <1991Jun27.150900.3043@oakhill.sps.mot.com> Reply-To: dant@ryptyde.UUCP (Daniel Tracy) Organization: Ryptyde Timesharing (ryptyde.cts.com) Lines: 18 Responding to the following: >Just for my information, what is the cache size in the 80486? I don't know if someone already answered this, I'm very behind on messages. Just to get this in the open so it can be corrected if wrong: The 486's cache is 8K, is 4-way set-associative, and operates in writethrough mode only. It also has bus snooping to detect DMA operations and update the cache accordingly. In contrast, the 68040's cache is seperated into two 4K "parallel" caches (what is "parallel" about them? Can they both be read on the same cycles? Or do they just "widen the bus" to the caches?). The 68040's cache is also 4-way set-associative (something I don't really understand well), has bus snooping, but it also has a writeback, or copyback mode which improves performance (by not copying data back to RAM until the bus isn't busy).