Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!samsung!uunet!stanford.edu!neon.Stanford.EDU!torrie From: torrie@cs.stanford.edu (Evan Torrie) Newsgroups: comp.sys.amiga.advocacy Subject: Re: 680x0 vs 80x86 Message-ID: <1991Jun29.190043.2072@neon.Stanford.EDU> Date: 29 Jun 91 19:00:43 GMT References: <92@ryptyde.UUCP> <4671.tnews@templar.actrix.gen.nz> <1154@stewart.UUCP> <1991Jun25.165516.13021@mintaka.lcs.mit.edu> <1991Jun27.064123.27492@neon.Stanford.EDU> <1991Jun27.150900.3043@oakhill.sps.mot.com> <132@ryptyde. Sender: torrie@neon.Stanford.EDU (Evan James Torrie) Organization: Computer Science Department, Stanford University, Ca , USA Lines: 28 dant@ryptyde.UUCP (Daniel Tracy) writes: >In contrast, the 68040's cache is seperated into two 4K "parallel" caches >(what is "parallel" about them? Can they both be read on the same cycles? Yes. Useful when your pipeline is overlapping EA Fetches with Instruction fetches. >The 68040's cache is also 4-way set-associative (something I don't really >understand well), Means that four memory addresses can map to the same cache-line without invalidating each other. Generally helps prevent pathological cases of program behaviour from destroying your hit ratio. >has bus snooping, but it also has a writeback, or copyback >mode which improves performance (by not copying data back to RAM until the bus >isn't busy). The nice thing about these on the 040 is that they are selectable on a page-by-page basis. So you can make some addresses (such as I/O addresses) non-cacheable, while ordinary code etc runs in copyback mode. -- ------------------------------------------------------------------------------ Evan Torrie. Stanford University, Class of 199? torrie@cs.stanford.edu "Lay me place and bake me pie, I'm starving for me gravy... Leave my shoes and door unlocked, I might just slip away - hey - just for the day."