Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!cs.utexas.edu!convex!texsun!cronkite!newstop!sun!amdcad!dvorak.amd.com!proton!tim From: tim@proton.amd.com (Tim Olson) Newsgroups: comp.sys.amiga.advocacy Subject: Re: 680x0 vs 80x86 Message-ID: <1991Jun30.015505.29020@dvorak.amd.com> Date: 30 Jun 91 01:55:05 GMT References: <1991Jun27.064123.27492@neon.Stanford.EDU> Sender: usenet@dvorak.amd.com (Usenet News) Reply-To: tim@amd.com (Tim Olson) Organization: Advanced Micro Devices, Austin, TX Lines: 25 In article kls30@DUTS.ccc.amdahl.com (PUT YOUR NAME HERE) writes: ^^^^^^^^^^^^^^^^^^ Have you done it, yet?? | The OS does not have to be aware of the cache unless it wants to turn it | on or off. The CPU has to intimately know the cache. The OS does not | need to know it is there. The OS needs to know about the TLB because the | OS will handle page faults, loading descriptor tables, and just overall | hadling of virtual memory. | | A cache should be transparent if someone tell you otherwise they are | mistaken. I've designed memory management and cache controller units. | The cache controller has always been transparent to the software. There are many different types of caching schemes. A frequently used scheme to speed up cache references (especially in instruction caches, where coherency is not an issue) is to use virtual addresses for the tag lookup and comparison. In this case, the OS must be aware of the cache and invalidate all or part of it on a change of virtual-to-physical mapping, which the OS controls. -- -- Tim Olson Advanced Micro Devices (tim@amd.com)