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From: dwgordon@matt.ksu.ksu.edu (Dwight W. Gordon)
Subject: Re: Memory Too FAST?!?!?!
Message-ID: <1991Jun26.114759.18270@maverick.ksu.ksu.edu>
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Date: Wed, 26 Jun 91 11:47:59 GMT
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hdrw@ibmpcug.co.uk (Howard Winter) writes:

>[about whether DRAM chips with a faster speed rating than needed should work]
>You are right, he is wrong - the speed rating is related to the time the chip
>needs for its output data to stabilise after the 'Read' signal is asserted
>(for the purists - this is s Gross Simplification).  Having chips
>that are too fast just means they sit around with valid data for
>longer - They should work perfectly.
>-Howard.

  Not exactly correct.  There is a possibility that the data may
become valid too soon.  I teach my students about microprocessor
timing in my courses.  One of the problems that can occur is
data latency from a previous device access.  Old data from some
other device may be on the bus at the same time that the RAM
data appears.  This causes a bus conflict.  This may manifest
itself in the form of a parity error.  (I used to consult for
a company that repaired IBM desktops.  Original IBM-PC/XTs used
a combinational logic design to detect parity.  Results were
sent to the NMI*.  Bus conflicts caused parity errors - sometimes.)
  With a reasonable design this problem is unlikely unless you
go overboard (<80nS parts in a board designed for 120nS).  These
numbers are just examples.  Without a complete timing analysis
of the system (which, I suspect, not even some manufacturers are
doing), there is no guarantee.

- Dwight -
--
Dwight W. Gordon, Ph.D.                     Kansas State University
dwgordon@matt.ksu.ksu.edu             Electrical and Computer Engineering
dwgordon@ksuvm.bitnet                             Durland Hall
Phone 913-532-5600; FAX 913-532-7810        Manhattan, KS 66506-5105