Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!samsung!olivea!uunet!mcsun!hp4nl!rulway.LeidenUniv.nl!rulcvx.LeidenUniv.nl!breemen From: breemen@rulcvx.LeidenUniv.nl (E. van Breemen) Newsgroups: comp.sys.m68k Subject: Help needed for DRAM interfacing on '020 board. Message-ID: <1991Jun29.190140.16168@rulway.LeidenUniv.nl> Date: 29 Jun 91 19:01:40 GMT Sender: root@rulway.LeidenUniv.nl (System PRIVILEGED Account) Organization: Leiden University, the Netherlands. Lines: 23 Nntp-Posting-Host: rulcvx.leidenuniv.nl Leiden, The Netherlands, Fri Jun 28 00:09:54 1991 Hello there, I recently completed an 68020 accelerator board for my Amiga. I am now planning to add 4 MB of 32 bits wide dynamic zero-wait-state memory. I want to use eight 1M x 4 memory chips. A good starting point is probably a relevant Motorola application note, so I contacted the Motorola representative in The Netherlands. They can only help me when I know exact numbers of their publications. My questions: I What relevant notes exist and what is their AN number? II Can anyone out there recommend me a general publication about dynamic RAM? Are there publications that deal with the '020? III Can anyone recommend me a DRAM controller I can use? All answers, hints and suggestions are very welcome. Thanks in advance! Greetings, Raymond Hoving.